.

( VICTOR. Architecture of Multiprocessor Complex
Preprint, Inst. Appl. Math., the Russian Academy of Science)

..
(V.M.Mihelev)

. ..

, 2002

. .

Abstract

A variant of computer multithreading architecture is described. It has a good look at problem of connection processors and a shared memory as well as synchronization of parallel execution.

 

 

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, [1,2]. Dynamic Multithreading Processor [3], Trace Processor [4,5] Tera computer system [6]. [1,2] , . .

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Flowchart: Manual Operation:

Flowchart: Manual Operation:

 

 

1

 

2

 

 

 

 

 

 

8.

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1. . .

add, sub, mult, div, mod .

or, and, not .

eq, ge, ne, le, lt, gt , . true false.

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fork - .

fork - .

 

gnr . , < >... 0. . , , gnr . , , gnr.

3. . .

br - .

cond . true, , false, .

4. , .

call - . .

par . . D.

5. , . , S.

rdv .

rdup rdv. , , up, .

wrv . - , rd.

wrup , rdup. wrv.

crd .

cwr .

push - C,D,E,F,G,H,S , .

pop , .

6. .

stop - .

7. .

emp .

 

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1. .

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MM,NN,RR: array[1..20] of integer;

Sum: integer;

 

For I in 1..20

Loop

For j in 1..20

Loop Sum:=0;

For k in 1..20

Loop Sum+=MM[i,k]*NN[k,j]

End loop;

RR[i,j]:=Sum

End loop

End loop

 

gnr , .

 

 

rdv l S 19 19 => S

gnr a end . à

 

mult l S 20

wtv r S D i*20 => D

rdv l S 19

gnr a Line à

 

wrv r S E j => E

rdv l F 0 k:=0 => F

rdv l C 0 C=0

Cycle eq r F 20

 

cond a Summa

rdv r H F

 

 

add r H D i*20+k => H

rdv a H MM

wrv r S G MM[j,k] => G

rdv r H 20

mult r H F

add r H E k*20+j => H

rdv a H NN NN[k,j] => S

mult r S G MM[i,k]*NN[k,j] => S

add r C S

add l F 1 k:=k+1

br a Cycle

 

Summa add r D E i*20+j => E

Rdv r S C

wrv a D RR RR[I,j]

stop

 

Line stop

 

End stop

, . à . => .

2. .

, , , . . , , . , , . 10 MM 1000 .

 

rdv l D 1 D = 0

rdv l S 10-1

gnr a End 10 à

 

Cycle eq l D 0

cond a Stp

rdv l D 0

rdv l E 0 E

rdup a E MM

wrv r S F F

 

Check add l E 1

rdup a E MM

wrv r S G G

le r F G

cond a Right

wrv r G H

rdv r F G

wrv r H F

rdv l D 1

Rignt rdv r S F

sub l E 1

wrup a E MM

add l E 1

rdv r F G

lt l E 1000-1

cond a Check

rdv r S G

wrup a E 0

br a Cycle

Stp stop

 

End stop

 

, gnr, , .

 

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Proc RlSign(x,y) returns integer (* *)

If x*y>0

then return 0

else return 1

end if;

 

p*RlSign(m,n) (* RlSign *)

 

m , n NN, p PP. , B. , .

C,D,E,F,G,H,S, . . , .

.

RlSign proc

RlSign#1 nop m

RlSign#2 mult w WRlSign n

WRlSign ,

gt l S 0 RlSign.

pop B 0

rdv l S 0

cond d D 0 D

rdv l S 1

br d D 0

endp

 

 

RlSign.

 

push c D 0

rdv l S Rt Rt => S

call c D 28

rdv l S RlSign

par c D 40

rdv l S RlSign#1

wrv c D 40

rdv a MM

fork d D 40

rdv l S RlSign#2

wrv c D 40

rdv a NN

fork d D 40

rdv a PP

Rt mult w Wmlt Wmlt ,

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1.     ..

,

. , 2000, N 59.

 

2.     ..

,

. , 2001, N 81.

 

3.     H. Akkary, M. Driscoll

A Dynamic Multithreading Processor.

31st Annual ACM/IEEE International Simposium on Microarchitecture,

Nov. 1998

 

4.     E. Rotenberg, Q. Jacson, Y. Sazeides, and J.Smith,

Trace Processor.

30st Annual ACM/IEEE International Simposium on Microarchitecture,

Dec. 1997

 

5.     James E. Smith and Sriram Vajapeyam

Trace Processor: Moving to Fourth-Generation Microarchitectures,

IEEE Computer, Vol. 30, No.9, September 1997.

 

6.     R. Alverson, D. Callaham, D. Cummings, B. Koblenz, A Portenfueld,

B. Smith.

The Tera computer system.

Proceedings of the ACM International Conference on Supercomputing,

June 1990.